In EEPROM or Flash EEPROM non-volatile memory devices, it is possible electrically to write, to read and to erase the elementary memory cells which constitute them: particularly, the erasure of the Flash EEPROM memories consists of an operation that lowers the threshold voltage value of the memory cells, extracting the negative charge stored in the floating gate.
Such an erasing operation can be performed by means of a technique wherein the source electrode of the memory cells is carried to a voltage level near the supply voltage and a negative voltage is applied to the control gate electrode, always keeping not connected the drain electrode.
The management of the voltage negative values in a circuit manufactured in CMOS technology can be difficult, because it can be not possible to apply negative voltages with suitable values to the source or drain electrodes of the N channel MOSFET, without forward biasing the source/substrate or drain/substrate junctions, the substrate of the integrated circuit being rigidly connected to ground.
Such a problem is solved using a CMOS technology which allows to insulate the bulk electrode of the N channel MOSFET transistors from the device substrate, necessarily connected to ground.
FIG. 1 shows, for example, the section view of a N channel MOS transistor manufactured in triple well technology, and FIG. 2 shows the circuit symbol which represents such transistor. In FIG. 1 there is a P type deep substrate 1 connected to ground, wherein a N type well 2 is obtained and it is connected to the supply voltage VDD; inside it there is another P type well 3 with two N+ doped zones corresponding to the drain and source electrodes; the well 3 electrode is connected to the source electrode. The substrate 1 and the wells 2 and 3 are connected to their external electrodes through contact regions which have a higher doping.
By means of this triple well technology the N channel MOSFET has such N well 2 that by applying positive supply voltage VDD to this well it is possible to inversely bias all the parasitic junctions existing inside the structure, even when negative voltages are applied to the source electrode, connected to the bulk electrode 3 of the same transistor.
It is desired, then, that inside the Flash EEPROM memory there are switching circuits able to supply out voltage values equal to the supply voltage and to the negative voltage, in order to allow the correct control of all the analogue circuitry.